1. Field of the Invention
The present invention relates to a transistor and a method of manufacturing the same. In particular, the present invention relates to a power MOSFET widely used in a power supply circuit or the like and a method of manufacturing the same.
2. Description of the Related Art
FIGS. 29 and 30 show a conventional trench type power MOSFET designated by reference numeral 101. FIG. 30 is a cross-sectional view taken along line Xxe2x80x94X in FIG. 29. It is noted that like component members are designated by like reference numerals in FIGS. 29 and 30.
This power MOSFET 101 has a semiconductor substrate constituted by successively forming a drain layer 112 composed of an nxe2x88x92-type epitaxial layer and a P-body region 113 on an n+-type silicon substrate 111 as shown in FIG. 30.
A plurality of trenches having a rectangular cross section of which bottom portion reaches the drain layer 112 are formed in the P-body region 113 and disposed in parallel to each other. A p+-type diffusion region 116 in a predetermined depth from the surface of the P-body region 113 is formed at a position between adjacent trenches. An n+-type source region 130 is formed in the periphery of the p+-type diffusion region 116 and surrounding an aperture of the trench from the surface of the P-body region 113 to such a depth as not reaching the drain layer 112.
A gate insulating film 124 is formed on an inner peripheral surface and bottom surface of the trench. A polysilicon gate 127 is formed on a surface of the gate insulating film 124 so that the inside of the trench is filled and that its upper end is positioned higher than the lower end of the source region 130.
A PSG (phospho-silicate glass) film 131 is formed on top of the polysilicon gate 127. A source electrode film 137 composed of aluminum is formed so as to cover the PSG film 131 and the surface of the semiconductor substrate. The polysilicon gate 127 and the source electrode film 137 are electrically insulated from each other by the PSG film 131. Furthermore, a drain electrode film 193 is formed on the bottom surface of the semiconductor substrate.
In a power MOSFET 101 having this structure, when a voltage equal to a threshold voltage or higher is applied between the polysilicon gate 127 and the source electrode film 137 in a state that a high voltage is being applied between the source electrode film 137 and the drain layer 112, an inversion layer is formed at an interface between the gate insulating film 124 and the P-body region 113. Thus, a current flows from the drain to the source through the inversion layer.
The abscissa axis (E) of a graph in FIG. 30 represents an electric field strength when reverse bias voltage is applied between the source electrode film 137 and the drain layer 112. The ordinate axis (y) represents a position on a line starting at an origin and vertically reaching the n+-type silicon substrate 111 where the origin is the surface of the source region 130 in the power MOSFET 101 shown in FIG. 30.
Line Yxe2x80x94Y in FIG. 30 is a line starting at one point in the source region 130 and vertically reaching the n+-type silicon substrate 111 through the P-body region 113 and the drain layer 112 without passing through the p+-type diffusion region 116. A polygonal line (b) in FIG. 30 is a graph showing the relationship between a position on line Yxe2x80x94Y and the electric field strength thereat.
As shown in FIG. 30, the electric field strength E includes a high electric field intensively applied to a portion of a pn junction formed by the P-body region 113 and the drain layer 112. To secure a desired avalanche breakdown voltage by decreasing the electric field strength, the concentration of the drain layer 112 can be lowered so that the depletion layer can be easily expanded. In this case, however, a problem arises that the on-resistance of the power MOSFET 101 increases.
The present invention was accomplished to solve the above-described problem of the prior art. Accordingly, an object of the present invention is to provide a technique by which the on-resistance RON of a transistor of the present invention can be made lower than that of a conventional one even when the transistor has a avalanche breakdown voltage equal to that of the conventional one.
To solve the above problem, a first aspect of the present invention is a transistor comprising a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type disposed on the semiconductor layer and an opposite conductive region of a second conductivity type disposed on the drain layer, polysilicon containing impurities of the second conductivity type disposed in part of the drain layer, a gate trench disposed from a surface of the opposite conductive region to the polysilicon, a source region of the first conductivity type formed on the surface of the opposite conductive region at a position adjacent to the gate trench, a gate insulating film positioned on the inner surface of the gate trench and disposed over the drain layer, the opposite conductive region and the source region, and a gate electrode film disposed in the gate trench in tight contact with the gate insulating film and insulated from the polysilicon.
A second aspect of the invention is a transistor according to the first aspect, wherein the polysilicon and the gate electrode film are insulated from each other by the gate insulating film.
A third aspect of the invention is a transistor according to the first aspect, further comprising an insulating film which is disposed between the polysilicon and the drain layer and insulates the polysilicon from the drain layer.
A fourth aspect of the invention is a transistor according to the first aspect, wherein the semiconductor layer is of the first conductivity type.
A fifth aspect of the invention is a transistor according to the first aspect, wherein the semiconductor layer is of the second conductivity type.
A sixth aspect of the invention is a transistor comprising a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type disposed on the semiconductor layer and an opposite conductive region of a second conductivity type disposed on the drain layer, a semiconductor material disposed in part of the drain layer and constituted so that a depletion layer can be formed therein, a gate trench disposed from a surface of the opposite conductive region to the semiconductor material, a source region of the first conductivity type formed on the surface of the opposite conductive region at a position adjacent to the gate trench, a gate insulating film positioned on the inner surface of the gate trench and disposed over the drain layer, the opposite conductive region and the source region, and a gate electrode film disposed in the gate trench in tight contact with the gate insulating film and insulated from the semiconductor material, wherein the semiconductor material is filled at the bottom of a deep trench disposed from the surface of the opposite conductive region to the inside of the drain layer, and the gate trench is formed by the surface of the semiconductor material and the inner peripheral surface of the deep trench.
A seventh aspect of the invention is a transistor according to the sixth aspect, wherein the semiconductor material and the gate electrode film are insulated from each other by the gate insulating film.
An eighth aspect of the invention is a transistor according to the sixth aspect, further comprising an insulating film provided on the inner wall surface and the bottom surface of the deep trench, and wherein the semiconductor material is filled at the bottom of the deep trench so as to come into tight contact with the insulating film.
A ninth aspect of the invention is a transistor according to the sixth aspect, wherein the semiconductor material is formed by epitaxial growth.
A tenth aspect of the invention is a transistor according to sixth aspect, wherein the semiconductor layer is of the first conductivity type.
An eleventh aspect of the invention is a transistor according to sixth aspect, wherein the semiconductor layer is of the second conductivity type.
A twelfth aspect of the invention is a method of manufacturing a transistor, comprising the steps of forming a deep trench in a semiconductor substrate having a drain layer of a first conductivity type and an opposite conductive region of a second conductivity type disposed on the drain layer from a surface of the opposite conductive region to the drain layer, filling a semiconductor material in the deep trench from the bottom surface of the deep trench to a depth not reaching the opposite conductive region to be constituted so that a depletion layer can be formed therein, forming a gate insulating film from the surface of the semiconductor material over the inner surface of the gate trench constituted by the surface of the semiconductor material and the deep trench, forming a gate electrode film in which impurities of the first conductivity type are diffused in the gate trench so as to come into tight contact with the gate insulating film, and forming a source region of the first conductivity type in the semiconductor substrate surface surrounding the gate trench.
A thirteen aspect of the invention is a method of manufacturing a transistor according to the twelfth aspect, wherein, the step of filling the semiconductor material in the deep trench comprises the steps of, forming an insulating film from the bottom surface of the deep trench to a depth not reaching the opposite conductive region, and forming the semiconductor material on the insulating film surface and filling the deep trench with the semiconductor material to the upper end of the insulating film.
A fourteenth aspect of the invention is a method of manufacturing a transistor according to the twelfth aspect, wherein the semiconductor material is formed by epitaxial growth and is composed of silicon containing impurities of the second conductivity type.
A fifteenth aspect of the invention is a method of manufacturing a transistor according to the twelfth aspect, wherein the semiconductor material is composed of polysilicon containing impurities of the second conductivity type.
According to a transistor of the present invention, polysilicon containing impurities is disposed under the gate trench filled with a gate electrode therein.
Therefore, the depletion layer is formed into the polysilicon under the gate electrode and is expanded from a region of the opposite conductivity type to a depth where the bottom surface of the polysilicon is positioned in the drain layer. Thus, the electric field strength in a depth direction inside the semiconductor substrate becomes uniform. Consequently, the electric field strength is weakened as compared with that in a conventional transistor since a high electric field is not intensively applied to a portion at a certain depth. Therefore, the avalanche breakdown voltage of the transistor becomes higher than that of a conventional one.
Since the concentration of impurities in the drain layer does not need to be lowered to secure a high avalanche breakdown voltage unlike in the case of a conventional transistor, the concentration of impurities in the drain layer can be made higher than that in the conventional one and thereby the on-resistance of the transistor can be reduced.
According to another transistor of the present invention, a semiconductor material in which a depletion layer can be formed is filled at the bottom of the deep trench. A gate insulating film is disposed in a gate trench constituted by the surface of the semiconductor material and the inner peripheral surface of the deep trench, and a gate electrode film is disposed on a surface of a gate insulating film so as to fill in the gate trench.
Therefore, the depletion layer is expanded from the opposite conductivity type region to a depth where the bottom surface of the semiconductor material is positioned. Therefore, electric field strengths in the depth direction in the inside of the semiconductor substrate become uniform.
Furthermore, according to a method of manufacturing a transistor of the present invention, a deep trench is formed and then a semiconductor material in which a depletion layer can be formed is filled at the bottom of the deep trench. Then, a gate insulating film is formed on the semiconductor material surface and an inner peripheral surface of a gate trench constituted by the semiconductor material surface and the inner peripheral surface of the deep trench. Then, a gate electrode film is formed in the gate trench so as to come into tight contact with the gate insulating film.
Therefore, since the polysilicon layer is easily formed under the gate electrode film in a state that the polysilicon layer and the gate electrode film are insulated from each other by the gate insulating film, the depletion layer can be formed in this polysilicon layer so that the electric field strengths in the drain layer can be made uniform.